New Through-Wafer Via Interconnections with Thick Oxidized Porous Silicon Sidewall Via

概要

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In this paper, we present the detailed fabrication process and high-frequency characterization of a new silicon through-wafer via interconnection and a low pass filter module flip-chip bonded to these via interconnections. An oxide liner of 18 μm thick for the via was fabricated on a complementary metal–oxide–semiconductor (CMOS)-grade low-resistivity 5 $\Omega$$\cdot$cm silicon wafer using the oxidized porous silicon (OPS) process. The through-wafer vias were filled with copper by electroplating. For a via interconnection of 240 μm length and 70 μm diameter, the series inductance and resistance are 0.079 nH and 0.059 $\Omega$ each. A coplanar waveguide (CPW) and a RF low pass filter (LPF) module were assembled on this through-wafer via interconnection substrate.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2006-08-15