A New Stacked-Mask Process Utilizing Spun-on Carbon Film for Sub-130-nm Etching
スポンサーリンク
概要
- 論文の詳細を見る
A novel stacked-mask process (S-MAP) was developed for sub-130-nm etching. The S-MAP consists of a tri-layer with a top layer of thin resist for patterning, a spin-on-glass (SOG) interlayer, and a newly developed spun-on carbon-film bottom layer. The spun-on carbon film was synthesized, in particular to have high carbon and low oxygen contents, and showed an etching resistivity 1.3 times higher than that of conventional resist films. An S-MAP utilizing this spun-on carbon film provides improved critical dimension (CD) control and enables etching of high-aspect-ratio holes. Via first dual damascene (DD) formation employing S-MAP eliminated the undesirable SiO2 fence around the top of the via holes, whereas the conventional process does not.
- 2003-10-15
著者
-
ABE Junko
Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company
-
HAYASHI Hisataka
Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company
-
KISHIGAMI Daizo
Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company
-
OHIWA Tokuhisa
Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company
-
Onishi Yasunobu
Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation
-
Sato Yasuhiko
Process & Manufacturing Engineering Center Toshiba Corporation Semiconductor Company
-
Shiobara Eishi
Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation
-
Hayashi Hisataka
Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company, 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa 235-8522, Japan
-
Ohiwa Tokuhisa
Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company, 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa 235-8522, Japan
-
Shibata Tsuyoshi
Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company, 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa 235-8522, Japan
-
Onishi Yasunobu
Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company, 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa 235-8522, Japan
-
Sato Yasuhiko
Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company, 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa 235-8522, Japan
-
Shiobara Eishi
Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company, 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa 235-8522, Japan
関連論文
- Highly Selective Si_3N_4/SiOC Etching Using Dual Frequency Superimposed RF Capacitively Coupled Plasma
- Optimization of Polysilane Structure as Fast-Etching Bottom Antireflective Coating for Deep Ultraviolet Lithography
- A New Stacked-Mask Process Utilizing Spun-on Carbon Film for Sub-130-nm Etching
- Application of Organic Silicon Clusters to Pattern Transfer Process for Deep UV Lithography
- Fabrication of Silicon-on-Nothing Structure by Substrate Engineering Using the Empty-Space-in-Silicon Formation Technique
- Application of Electron Beam Cured Spin-On Glass to Trilevel Resist System for Deep and Vacuum Ultraviolet Lithography
- Sub-45 nm SiO2 Etching with Stacked-Mask Process Using High-Bias-Frequency Dual-Frequency-Superimposed RF Capacitively Coupled Plasma
- Highly Selective Si3N4/SiOC Etching Using Dual Frequency Superimposed RF Capacitively Coupled Plasma
- Dual-Frequency Superimposed RF Capacitive-Coupled Plasma Etch Process
- Organic Film Reactive Ion Etching Using 100 MHz rf Capacitive Coupled Plasma
- Sub-55 nm Etch Process Using Stacked-Mask Process
- A New Stacked-Mask Process Utilizing Spun-on Carbon Film for Sub-130-nm Etching
- Ultrathin Resist Pattern Transfer Process by Filling Mask Material in the Resist Pattern
- Application of Electron Beam Cured Spin-On Glass to Trilevel Resist System for Deep and Vacuum Ultraviolet Lithography