A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS
スポンサーリンク
概要
- 論文の詳細を見る
Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).
- 2001-04-30
著者
-
Fujino Seiji
Electronics Device R&d Center Denso Corporation
-
WATANABE Takamoto
R&D Department, Denso Corporation
-
Ishihara Hideaki
Ic Engineering Department 1 Denso Coroporation
-
Abe Hirofumi
Ic Engineering Department 1 Denso Corporation
-
Mizuno Shoji
Electronics Device R&d Center Denso Corporation
-
Higuchi Yasushi
Electronics Device R&d Center Denso Corporation
-
Fukumoto Harutsugu
Research Laboratories Denso Corporation
-
Shirakawa Isao
Department Of Electronic Engineering University Of Osaka
-
Shirakawa Isao
Department of Information System Engineering, Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita-shi, Osaka 565-0871, Japan
-
Kawamoto Kazunori
Electronics Device R&D Center, Denso Corporation, 5 Maruyama, Ashinoya, Kouta-cho, Nukata-gun, Aichi 444-0193, Japan
-
Fukumoto Harutsugu
Research Laboratories, Denso Corporation, 500-1 Komenoki, Nissin-shi, Aich 470-0011, Japan
-
Fujino Seiji
Electronics Device R&D Center, Denso Corporation, 5 Maruyama, Ashinoya, Kouta-cho, Nukata-gun, Aichi 444-0193, Japan
-
Watanabe Takamoto
R&D Department, Denso Corporation, 1-1 Syouwa-cho, Kariya-shi, Aich 448-8661, Japan
-
Higuchi Yasushi
Electronics Device R&D Center, Denso Corporation, 5 Maruyama, Ashinoya, Kouta-cho, Nukata-gun, Aichi 444-0193, Japan
-
Mizuno Shoji
Electronics Device R&D Center, Denso Corporation, 5 Maruyama, Ashinoya, Kouta-cho, Nukata-gun, Aichi 444-0193, Japan
-
Abe Hirofumi
IC Engineering Department 1, Denso Corporation, 5 Maruyama, Ashinoya, Kouta-cho, Nukata-gun, Aichi 444-0193, Japan
関連論文
- Threshold Voltage Control Using Floating Back Gate for Ultra-Thin-Film SOI CMOS
- Silicon Wafer Direct Bonding through the Amorphous Layer
- Silicon Wafer Direct Bonding without Hydrophilic Native Oxides
- Reduced Urination Rate while Drinking Beer with an Unpleasant Taste and Off-flavor
- Correlation between the Drinkability of Beer and Gastric Emptying
- A 25kV ESD Proof LDMOSFET with a Turn-on Discharge MOSFET
- A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS
- A 200V CMOS SOI IC with Field-Plate Trench Isolation for EL Displays
- A Single Chip Automotive Control LSI Using SOI BiCDMOS
- A Wireless Data System Constructed of SAW-Devices and Its Applications to Medical Cares
- Intelligent Power IC with Partial SOI Structure
- A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells
- Wireless Digital Video Transmission System Using IEEE802.11b PHY with Error Correction Block Based ARQ Protocol(Special Issue on Mobile Multimedia Communications)
- 200 V Rating CMOS Transistor Structure with Intrinsic SOI Substrate
- Analysis of Self-Heating in SOI High Voltage MOS Transistor (Special Issue on SOI Devices and Their Process Technologies)
- Performance Estimation at Architecture Level for Embedded Systems(Special Section on VLSI Design and CAD Algorithms)
- Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic (特集 電子システムの設計技術と設計自動化)
- Low-Power Scheme of NMOS 4-Phase Dynamic Logic (Special Issue on Integrated Electronics and New System Paradigms)
- Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Implementation of Java Accelerator for High-Performance Embedded Systems
- An Algorithm for Generating All The Directed Paths and Its Application
- A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS