200 V Rating CMOS Transistor Structure with Intrinsic SOI Substrate

スポンサーリンク

概要

• 論文の詳細を見る

• The subject of this study is to propose a new structure that can realize simultaneously high breakdown voltage and high packing density for both Nch low side switch and Pch high side switch in 200 V class rating. As the conventional techniques for the electric field relaxation, the structure of field plate, field ring and RESURF are well known, but these techniques are inadequate for the high packing density because they are the techniques in surface region. In order to conquer this subject, it is necessary to relax the electric field in the deep region. The electric field relaxation was investigated by device simulation. In the Nch low side switch the electric field is relaxed by buried oxide film in SOI structure. However, electric field relaxation cannot be realized only by adapting the SOI structure for Pch high side switch. Then we tried to insert an intrinsic layer between P-drift layer and the buried oxide film in order to spread the depletion layer in the deep region. This spread depletion layer by intrinsic layer and the depletion layer by field plate connect vertically, and the dosage of the ion implantation for drift layer can be set to two times higher than the case without intrinsic layer. As the results, it was revealed that the SOI structure with intrinsic layer is effective to achieve this subject. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250 V were achieved.

• 社団法人電子情報通信学会の論文
• 2000-12-25

著者

• YAMAGUCHI Hitoshi

  Research Laboratories, Nippondenso Cooperation., Ltd.

• Himi H

  Denso Corporation

• Himi Hiroaki

  Research Laboratories Nippondenso Co. Ltd.

• KAWAMOTO Kazunori

  DENSO CORPORATION

• KAWAMOTO Kazunori

  Electronics Device R&D Center, Denso Corporation

• YAMAGUCHI Hitoshi

  DENSO CORPORATION

• Yamaguchi H

  Nec Corp. Sagamihara‐shi Jpn

• AKITA Shigeyuki

  Research Laboratories, DENSO CORPORATION

• HIMI Hiroaki

  Electronics Device Product Division, DENSO CORPORATION

• Akita Shigeyuki

  Research Laboratories Denso Corporation

• Higuchi Y

  Electronics Device R&d Center Denso Corporation

• Higuchi Yasushi

  Electronics Device R&d Center Denso Corporation

• Kawamoto K

  Electronics Device R&d Center Denso Corporation

• Kawamoto Kazunori

  Electronics Device R&D Center, Denso Corporation, 5 Maruyama, Ashinoya, Kouta-cho, Nukata-gun, Aichi 444-0193, Japan

関連論文

• Superjunction by Wafer Direct Bonding
• Silicon Wafer Direct Bonding without Hydrophilic Native Oxides
• A 25kV ESD Proof LDMOSFET with a Turn-on Discharge MOSFET
• A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS
• A 200V CMOS SOI IC with Field-Plate Trench Isolation for EL Displays
• A Single Chip Automotive Control LSI Using SOI BiCDMOS
• Intelligent Power IC with Partial SOI Structure
• 200 V Rating CMOS Transistor Structure with Intrinsic SOI Substrate
• Analysis of Self-Heating in SOI High Voltage MOS Transistor (Special Issue on SOI Devices and Their Process Technologies)
• Development of time-to-digital converter IC for laser radar
• A CMOS Time-to-Digital Converter LSI with Half-Nanosecond Resolution Using a Ring Gate Delay Line (Special Issue on ASICs for Automotive Electronics)
• A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

もっと見る 閉じる

スポンサーリンク