Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays(Parasitics and Noise)(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.

• 社団法人電子情報通信学会の論文
• 2003-12-01

著者

• Imai Shigeki

  Sharp Corp. Tenri‐shi Jpn

• Shirakawa Isao

  Department Of Information System Engineering Graduate School Of Engineering Osaka University

• UCHIDA Yoshihiro

  Department of Breast Surgery, Cancer Institute Hospital

• Uchida Yoshihiro

  Department Of Information Systems Engineering Osaka University

• Uchida Yoshihiro

  Department Of Bioproduction Faculty Of Agriculture Yamagata University

• Imai Shigeki

  Sharp Corporation

• Kubota Y

  Sharp Corporation

• Tsukiyama Shuji

  Faculty Of Science And Engineering Chuo University

• TANI Sadahiro

  Department of Information Systems Engineering

• FURUIE Makoto

  Synthesis Corporation

• LEE BuYeol

  SHARP Corporation

• NISHI Shuji

  SHARP Corporation

• KUBOTA Yasushi

  SHARP Corporation

• Tani Sadahiro

  Department Of Information Systems Engineering:sharp Corporation

• Shirakawa Isao

  Department Of Electronic Engineering University Of Osaka

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