A 1.0-V 12-bit Digitally Calibrated SAR ADC Using Hybrid DAC Technique
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概要
- 論文の詳細を見る
A 1.0-V, 12-bit, 80-MS/s two time-interleaved successive approximation register (SAR) ADC with 1.2-V differential full-scale voltage is presented. To minimize the circuit area, ahybrid DAC which consists of the capacitor and the resistor DACs is proposed, where the resistor DAC has little impact onthe area, 6%. On-chip logic calibrates errors of the DAC in the individual channels and the channel-to-channel gain error and offset. The ADC achieves 61.8 dB peak SNDR and 78.8 dB peak SFDR at 80-MS/s and consumes 10.7 mW (6.8 mW, excluding a reference voltage generator). Over 60 dB SNDR is achieved among all measured chips.
- 一般社団法人電子情報通信学会の論文
- 2013-06-27
著者
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Itakura Tetsuro
Toshiba
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Ishii Hirotomo
Toshiba Corporation Semiconductor Company
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SHIOCHI Masazumi
Toshiba Corporation
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Itakura Tetsuro
Toshiba Corporation
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Furuta Masanori
Toshiba Corporation
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Sugimoto Tomohiko
Toshiba Corporation
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Okawa Toru
Toshiba Corporation
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Ishii Hirotomo
Toshiba Corporation
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- A 1.0-V 12-bit Digitally Calibrated SAR ADC Using Hybrid DAC Technique
- A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique
- A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique