A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique
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概要
- 論文の詳細を見る
An eight-channel time-interleaved ADC with individual reference voltage buffers is presented. Each channel consists of buffer amplifier and two successive approximation ADC (SAR ADC) in a pipeline configuration. The proposed architecture shares an amplifier between the voltage buffer and the residue amplifier. The amplifier sharing technique achieves better isolation between the individual channels while minimizing the additional circuit. Over one bit redundancy is implemented to compensate the process variation of the MOM capacitance. Fabricated in 65nm CMOS with an active area of 0.36mm^2, the prototype chip achieves a peak SNDR of 32.3dB(single-channel) at 60MS/s and 26dB(time-interleave) at 480MS/s sampling rate and has a power consumption of 6mW.
- 2012-03-01
著者
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FURUTA Masanori
Toshiba Corporation Mobile Communication Laboratory
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Itakura Tetsuro
Toshiba
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Itakura Tetsuro
Toshiba Corporation
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Ogawa Taichi
Toshiba Corporation
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Furuta Masanori
Toshiba Corporation
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- A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique
- A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique