Low-Power Design of High-Speed A/D Converters(Analog, <Special Section>Low-Power LSI and Low-Power IP)

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概要

• 論文の詳細を見る

• In this paper, low-power design techniques of high-speed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A systematic approach to the power optimization of pipeline and parallel pipeline ADC's is introduced based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC. Finally, the theoretical minimum of required power as functions of the sampling rate, resolution and SNR is discussed. The analysis shows that, with the developments of new circuits and systems to approach to the minimum, the power can be further reduced by a factor of more than 1/10 without changing the basic architectures.

• 社団法人電子情報通信学会の論文
• 2005-04-01

著者

• FURUTA Masanori

  Toshiba Corporation Mobile Communication Laboratory

• Miyazaki Daisuke

  Research Institute Of Electronics Shizuoka University

• Kawai Nobuhiro

  The Authors Are With Graduate School Of Electronic Science And Technology Shizuoka University

• Honda Kazutaka

  Graduate School Of Electronic Science And Techonology Shizuoka University

• KAWAHITO Shoji

  The authors are with Research Institute of Electronics, Shizuoka University

• HONDA Kazutaka

  The authors are with Graduate School of Electronic Science and Technology, Shizuoka University

• FURUTA Masanori

  The authors are with Research Institute of Electronics, Shizuoka University

• MIYAZAKI Daisuke

  The authors are with Research Institute of Electronics, Shizuoka University

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• Low-Power Design of High-Speed A/D Converters(Analog, Low-Power LSI and Low-Power IP)
• A Digital Calibration Technique of Capacitor Mismatch for Pipelined Analog-to-Digital Converters(Special Issue on High-Performance Analog Integrated Circuits)
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