Leakage Analysis of DPA Countermeasures at the Logic Level(Side Channel Attacks,<Special Section>Cryptography and Information Security)
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概要
- 論文の詳細を見る
In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally applicable to various actual devices for simulating power analysis. Furthermore, we demonstrate the weakness of previously known hardware countermeasures for both our model and FPGA and suggest secure conditions for the hardware countermeasure.
- 社団法人電子情報通信学会の論文
- 2007-01-01
著者
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SUZUKI Daisuke
Information Technology R&D Center, Mitsubishi Electric Corporation
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Ichikawa Tetsuya
Kamakura Office Mitsubishi Electric Engineering Company Limited
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SAEKI Minoru
Information Technology R & D Center, Mitsubishi Electric Corporation
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Saeki Minoru
Information Technology R&d Center Mitsubishi Electric Corporation
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Suzuki Daisuke
Information Technology R&d Center Mitsubishi Electric Corporation
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Suzuki Daisuke
Information Technology R & D Center Mitsubishi Electric Corporation
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Suzuki Daisuke
Information Technol. R&d Center Mitsubishi Electric Corp.
関連論文
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