Random Switching Logic : A New Countermeasure against DPA and Second-Order DPA at the Logic Level(Side Channel Attacks,<Special Section>Cryptography and Information Security)
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概要
- 論文の詳細を見る
This paper proposes a new countermeasure, Random Switching Logic (RSL), against DPA (Differential Power Analysis) and Second-Order DPA at the logic level. RSL makes a signal transition uniform at each gate and suppresses the propagation of glitch to allow power consumption to be independent of predictable data. Furthermore, we implement basic logic circuits on the FPGA (Field Programmable Gate Array) by using RSL, and evaluate the effectiveness. As a result, we confirm the fact that the secure circuit can be structured against DPA and Second-Order DPA.
- 社団法人電子情報通信学会の論文
- 2007-01-01
著者
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SUZUKI Daisuke
Information Technology R&D Center, Mitsubishi Electric Corporation
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Ichikawa Tetsuya
Kamakura Office Mitsubishi Electric Engineering Company Limited
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SAEKI Minoru
Information Technology R & D Center, Mitsubishi Electric Corporation
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Saeki Minoru
Information Technology R&d Center Mitsubishi Electric Corporation
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Suzuki Daisuke
Information Technology R&d Center Mitsubishi Electric Corporation
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Suzuki Daisuke
Information Technology R & D Center Mitsubishi Electric Corporation
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Suzuki Daisuke
Information Technol. R&d Center Mitsubishi Electric Corp.
関連論文
- How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation
- How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation
- A Design Methodology for a DPA-Resistant Circuit with RSL Techniques
- How to Decide Selection Functions for Power Analysis : From the Viewpoint of Hardware Architecture of Block Ciphers
- Leakage Analysis of DPA Countermeasures at the Logic Level(Side Channel Attacks,Cryptography and Information Security)
- Random Switching Logic : A New Countermeasure against DPA and Second-Order DPA at the Logic Level(Side Channel Attacks,Cryptography and Information Security)
- High-Speed Passphrase Search System for PGP
- Security Evaluations of MRSL and DRSL Considering Signal Delays
- An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style
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