Reducing power of TLB with power-gating technique on microprocessor (計算機アーキテクチャ・2008年並列/分散/協調処理に関する『佐賀』サマー・ワークショップ(SWoPP佐賀2008)--研究会・連続同時開催)

概要

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The TLB (translation lookaside buffer) is the hardware that translates the virtual address used by program to the physical address, which accesses memory. This high associate structure consumes considerable power of the microprocessor about 16%. The leakage of register file is also a problem, while prior work only has looked into reducing dynamic power of TLB. In this paper, we use fine-grained RTPG (run-time power gating) technique to reducing TLB leakage power. The main idea is: for iTLB, using a recently accessing register to save the sequential accessed entry, then power-off the whole iTLB file; for dTLB using counters on every entry, when counters exceeds a threshold power-off that entry line. Results with a suite of Mibench mark shows that with the methods, for iTLB 67% leakage power can be saved, for dTLB 41% leakage power can be saved. Despite the small increase of miss rates, the approach can reduce leakage power of TLBs, without damaging the performance of microprocessors.
一般社団法人情報処理学会の論文
2008-07-29