Cache controller design with run-time power gating (計算機アーキテクチャ・2008年並列/分散/協調処理に関する『佐賀』サマー・ワークショップ(SWoPP佐賀2008)--研究会・連続同時開催)

スポンサーリンク

概要

• 論文の詳細を見る

• A leakage-efficient cache controller design is presented in this paper. The key insight is that a large circuits subset is accessed only when cache misses happen. By utilizing the run-time power gating technique, such a subset can be dynamically powered-off as a power gated domain. Two simple but effective sleeping control polices are proposed to assure the final leakage reduction effect; and to eliminate the impact of wake-up process, a latency concellation mechanism is also proposed. Evaluation results show, in 90nm CMOS technology, 69% and 64% of leakage power can be reduced for instruction cache controller and data cache controller without performance degradation.

• 一般社団法人情報処理学会の論文
• 2008-07-29

著者

• Amano Hideharu

  慶大

• Zhao Lei

  Graduate School Of Science And Technology Keio University

• ZHAO LEI

  慶大

• HUI XU

  慶大

• SEKI NAOMI

  慶大

• SAITO YOSHIKI

  慶大

• HASEGAWA YOHEI

  慶大

• USAMI KIMIYOSHI

  芝浦工大

• Hui Xu

  Graduate School Of Science And Technology Keio University

関連論文

• Cache controller design with run-time power gating (計算機アーキテクチャ・2008年並列/分散/協調処理に関する『佐賀』サマー・ワークショップ(SWoPP佐賀2008)--研究会・連続同時開催)
• Reducing power of TLB with power-gating technique on microprocessor (計算機アーキテクチャ・2008年並列/分散/協調処理に関する『佐賀』サマー・ワークショップ(SWoPP佐賀2008)--研究会・連続同時開催)
• Leakage Efficient TLB Design for Embedded Processors
• Performance Evaluation of Hardware Multi-process Execution on the Dynamically Reconfigurable Processor
• A Leakage Efficient Data TLB Design for Embedded Processors
• A Leakage Efficient Instruction TLB Design for Embedded Processors

スポンサーリンク