Performance Evaluation of Hardware Multi-process Execution on the Dynamically Reconfigurable Processor
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概要
- 論文の詳細を見る
The hardware multi-process execution is a technique to enhance throughput by dividing a reconfigurable device into several pieces and execute several processes in parallel. The hardware multi-process execution on Dynamically Reconfigurable Processor (DRP), which is a coarse grain reconfigurable processor developed by NEC Electronics, is implemented and evaluated with real applications, which can be divided into two categories: a single task like DCT or Viterbi decoder, and multi tasks like a JPEG encoder. An application is divided into small processes and implemented on a limited area of PE array. Inter-process communication is done through the embedded FIFO. Through the evaluation, the overhead of this modification is not so influenced to the performance, cost and power consumption. When the pipelined execution works well, the throughput is improved almost double.
- 社団法人電子情報通信学会の論文
- 2006-09-08
著者
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AMANO Hideharu
Keio University
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Amano Hideharu
慶大
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Amano Hideharu
Keio Univ.
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Tuan Vu
Keio Univ. Yokohama Jpn
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Katsura Naohiro
Graduate School Of Science And Technology Keio University
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Katsura Naohiro
Keio Univ. Yokohama Jpn
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Hasegawa Yohei
Keio University
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Hasegawa Yohei
Keio Univ.
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