Leakage Efficient TLB Design for Embedded Processors

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概要

• 論文の詳細を見る

• This paper presents a leakage-efficient TLB (Translation Lookaside Buffer) design for embedded processors. By utilizing the spatial and temporary locality of TLB references, the unused entries or even the whole TLB can be put into a low power mode by dynamic voltage scaling technique. According to their different accessing patterns, two leakage control mechanisms are proposed for instruction TLB and data TLB respectively. Evaluation results with six MiBench programs show that the proposed design can reduce 50% and 35% leakage power of instruction TLB and data TLB on average, with only 0.01% performance degradation.

• 一般社団法人情報処理学会の論文
• 2009-07-28

著者

• Zhao Lei

  Graduate School Of Science And Technology Keio University

• Hui Xu

  Graduate School Of Science And Technology Keio University

• Daisuke Ikebchi

  Graduate School of Science and Technology, Keio University

• Toshiaki Kamata

  Graduate School of Science and Technology, Keio University

• Mitaro Namiki

  Department of Computer and Information Sciences,Tokyo University of Agriculture and Technology

• Hideharu Amano

  Graduate School of Science and Technology, Keio University

• Xu Hui

  Graduate School Of Science And Technology Keio University

• Mitaro Namiki

  Department Of Computer And Information Sciences Tokyo University Of Agriculture And Technology

• Hideharu Amano

  Graduate School Of Science And Technology Keio University

• Toshiaki Kamata

  Graduate School Of Science And Technology Keio University

• Daisuke Ikebchi

  Graduate School Of Science And Technology Keio University

• Zhao Lei

  Keio University | Graduate School of Information Systems, University of Electro-Communications

• Daisuke Ikebuchi

  Keio University

• Zhao Lei

  Graduate School of Science and Technology, Keio University

関連論文

• Cache controller design with run-time power gating (計算機アーキテクチャ・2008年並列/分散/協調処理に関する『佐賀』サマー・ワークショップ(SWoPP佐賀2008)--研究会・連続同時開催)
• Reducing power of TLB with power-gating technique on microprocessor (計算機アーキテクチャ・2008年並列/分散/協調処理に関する『佐賀』サマー・ワークショップ(SWoPP佐賀2008)--研究会・連続同時開催)
• Leakage Efficient TLB Design for Embedded Processors
• An On/Off Link Regulation for Low-Power InfiniBand
• Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

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