Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

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概要

• 論文の詳細を見る

• In this paper, we present a prototype MIPS R3000 processor, which integrates the fine-grained power gating technique into its functional units. To reduce the leakage power consumption, functional units, such as multiplier and divider can be power-gated individually according to the workload of the execution program. The prototype chip -- Geyser-1 has been implemented with Fujitsu's 65nm CMOS technology; and to facilitate the design process with fine-grained power gating, a fully automated design flow has also been proposed. Comprehensive real-chip evaluations have been performed to verify the leakage reduction efficiency. According the evaluation results with benchmark programs, the fine-grained power gating can reduce the power of the processor by 5% at 25℃ and 23% at 80℃.

• 一般社団法人情報処理学会の論文
• 2011-08-10

著者

• Hideharu Amano

  Graduate School of Science and Technology, Keio University

• Mitaro Namiki

  Tokyo University of Agriculture and Technology

• Hideharu Amano

  Keio University

• Zhao Lei

  Keio University | Graduate School of Information Systems, University of Electro-Communications

• Daisuke Ikebuchi

  Keio University

• Kimiyoshi Usami

  Shibaura Institute of Technology

• Masaaki Kondo

  Graduate School of Information Systems, University of Electro-Communications

• Hiroshi Nakamura

  The University of Tokyo

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