Investigation of wafer warpage resulted from deep trench isolation in multi-layered SOI (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

概要

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In this paper, the wafer warpage that originated from the stress of DTI(deep trench isolation) is investigated. The wafer warpage resulted from oxide filled DTI with 4μm width and 40μm depth is simulated and measured. The DTI using mixed layer of 1μm thermal oxide and 0.8μm poly silicon is also considered. The wafer warpages from the room temperature to 500℃ are measured and analyzed. It is verified that the main source of the wafer warpage is the thermal stress. The wafer warpages of these DTIs at the room temperature are simulated and compared with the measured values. The difference between two values is less than 5%.
社団法人電子情報通信学会の論文
2007-06-18