Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits (Low Power Techniques, <Special Section> VLSI Design Technology in the Sub-100nm Era)

概要

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To drastically reduce the dynamic power (P_<AT>) and the leakage power (P_<ST>) of the CMOS MPEG4/H.264 motion estimation (ME) circuits, several power reduction techniques were developed. They were circuit architectures, which were able to reduce the supply voltages (V_<DD>) and numbers of logic gates of not only the whole circuit but the critical path, a fast motion estimation algorithm, and a leakage current reduction circuit. A 0.18-μm CMOS ME circuit has been fabricated by adopting those techniques. At a clock frequency of 160MHz and V_<DD> of 1.25 V, PAT decreased to 75.9μW, which was 5.35% that of a conventional ME circuit. P_<ST> also decreased to 0.82 nW, which was 3.93% that of the conventional ME circuit.
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