Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits (Low Power Techniques, <Special Section> VLSI Design Technology in the Sub-100nm Era)
スポンサーリンク
概要
- 論文の詳細を見る
To drastically reduce the dynamic power (P_<AT>) and the leakage power (P_<ST>) of the CMOS MPEG4/H.264 motion estimation (ME) circuits, several power reduction techniques were developed. They were circuit architectures, which were able to reduce the supply voltages (V_<DD>) and numbers of logic gates of not only the whole circuit but the critical path, a fast motion estimation algorithm, and a leakage current reduction circuit. A 0.18-μm CMOS ME circuit has been fabricated by adopting those techniques. At a clock frequency of 160MHz and V_<DD> of 1.25 V, PAT decreased to 75.9μW, which was 5.35% that of a conventional ME circuit. P_<ST> also decreased to 0.82 nW, which was 3.93% that of the conventional ME circuit.
- 社団法人電子情報通信学会の論文
著者
-
Kobayashi Nobuaki
Chuo Univ. Tokyo Jpn
-
Enomoto Tadayoshi
Faculty Of Science & Engineering Chuo University
-
Enomoto Tadayoshi
Chuo University
-
Enomoto Tadayoshi
Chuo Univ. Tokyo Jpn
-
EI Tomomi
Chuo University
-
Ei Tomomi
Faculty Of Science & Engineering Chuo University
-
Enomoto Tadayoshi
Chuo Univ.
関連論文
- A Low Dynamic Power 90-nm CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling Scheme and Fast Motion Estimation Algorithm Called Adaptively Assigned Breaking-off Condition Search(International Workshop on Advanced Image Tec
- Design of a 3.2 GHz 50 mW 0.5μm GaAs PLL-Based Clock Generator with 1 V Power Supply (Special Issue on Multimedia, Analog and Processing LSIs)
- Low-Voltage, Low-Power, High-Speed 0.25-μm GaAs HEMT Delay Flip-Flops
- A Multiple Block-matching Step (MBS) Algorithm for H.26x/MPEG4 Motion Estimation and a Low-Power CMOS Absolute Differential Accumulator Circuit(Digital,Low-Power, High-Speed LSIs and Related Technologies)
- Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
- Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit
- High-Throughput Technologies for Video Signal Processor (VSP) LSIs (Special Issue on Ultra-High-Speed LSIs)
- Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array
- Designs of Building Blocks for High-Speed, Low-Power Processors(Special Issue on High-Performance and Low-Power Microprocessors)
- FOREWORD (Special Issue on Low-Power LSI Technologies)
- A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called "Adaptively Assigned Breaking-Off Condition (A2BC)"
- A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called "Adaptively Assigned Breaking-Off Condition (A^2BC)"