A Low Dynamic Power 90-nm CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling Scheme and Fast Motion Estimation Algorithm Called Adaptively Assigned Breaking-off Condition Search(International Workshop on Advanced Image Tec
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概要
- 論文の詳細を見る
A 90-nm CMOS motion estimation(ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage (V_D) and the optimum clock frequency (f_c) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to 31.5μW, which was only 2.8% that of a conventional ME processor.
- 社団法人電子情報通信学会の論文
- 2009-01-05
著者
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Kobayashi Nobuaki
Chuo Univ. Tokyo Jpn
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Kobayashi Nobuaki
Chuo University Graduate School Of Science And Engineering Information And System Engineering Course
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Enomoto Tadayoshi
Chuo University
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Enomoto Tadayoshi
Chuo University Graduate School Of Science And Engineering Information And System Engineering Course
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Enomoto Tadayoshi
Chuo Univ. Tokyo Jpn
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Enomoto Tadayoshi
Chuo Univ.
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