A Multiple Block-matching Step (MBS) Algorithm for H.26x/MPEG4 Motion Estimation and a Low-Power CMOS Absolute Differential Accumulator Circuit(Digital,<Special Section>Low-Power, High-Speed LSIs and Related Technologies)
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概要
- 論文の詳細を見る
To drastically reduce the power dissipation (P) of an absolute difference accumulation (ADA) circuit for H.26x/MPEG4 motion estimation, a fast block-matching (BM) algorithm called the Multiple Block-matching Step (MBS) algorithm has been developed. The MBS algorithm can drastically improve the block matching speed, while achieving the same visual quality as that of a full search (FS) BM algorithm. Power dissipation (P) of a 0.18-μm CMOS absolute difference accumulator (ADA) circuit employing the MBS algorithm is significantly reduced to the range of about 0.3% to 12% that of the same ADA circuit adopting FS.
- 社団法人電子情報通信学会の論文
- 2007-04-01
著者
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Kobayashi Nobuaki
Chuo Univ. Tokyo Jpn
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Kobayashi Nobuaki
Faculty Of Science & Engineering Chuo University
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Enomoto Tadayoshi
Faculty Of Science & Engineering Chuo University
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EI Tomomi
Faculty of Science & Engineering, Chuo University
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Ei Tomomi
Faculty Of Science & Engineering Chuo University
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- A Multiple Block-matching Step (MBS) Algorithm for H.26x/MPEG4 Motion Estimation and a Low-Power CMOS Absolute Differential Accumulator Circuit(Digital,Low-Power, High-Speed LSIs and Related Technologies)
- Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
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- High-Throughput Technologies for Video Signal Processor (VSP) LSIs (Special Issue on Ultra-High-Speed LSIs)
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- A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called "Adaptively Assigned Breaking-Off Condition (A^2BC)"