Design of a 3.2 GHz 50 mW 0.5μm GaAs PLL-Based Clock Generator with 1 V Power Supply (Special Issue on Multimedia, Analog and Processing LSIs)

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A 3.2 GHz, 50 mW, 1 V, GaAs clock pulse generator (CG) based on a phase-locked loop (PLL) circuit has been designed for use as an on-chip clock generator in future high speed processor LSIs. 0.5μm GaAs MESFET and DCFL circuit technologies have been used for the CG, which consists of 224 MESFETs. An "enhanced charge-up current" inverter has been specially designed for a low power and high speed voltage controlled oscillator (VCO). In this new inverter, a voltage controlled dMESFET is combined in parallel with the load dMESFET of a conventional DCFL inverter. This voltage controlled dMESFET produces an additional charge-up current resulting in the new VCO obtaining a much higher oscillation frequency than that of a ring oscillator produced with a conventional inverter. With a single 1 V power supply (V_<dd>), SPICE calculation results showed that the VCO tuning range was 2.25 GHz to 3.65 GHz and that the average VCO gain was approximately 1.4 GHz/V in the range of a control voltage (V_C) from 0 to 1 V. Simulation also indicated that at a V_<dd> of 1 V the CG locked on a 50 MHz external clock and generated a 3.2 GHz internal clock (=50 MHz×64). The jitter and power dissipation of the CG at 3.2 GHz oscillation and a V_<dd> of 1 V were less than 8.75 psec and 50 mW, respectively. The typical lock range was 2.90 GHz to 3.59 GHz which corresponded to a pull-in range of 45.3 MHz to 56.2 MHz.
1994-12-25