Designs of Building Blocks for High-Speed, Low-Power Processors(<特集>Special Issue on High-Performance and Low-Power Microprocessors)

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概要

• 論文の詳細を見る

• A fast, low-power 16-bit adder, 32-word register file and 512-bit cache SRAM have been developed using 0.25-μm GaAs HEMT technology for future multi-GHz processors. The 16-bit adder, which uses a negative logic binary look-ahead carry structure based on NOR gates, operates at the maximum clock frequency of 1.67GHz and consumes 134.4mW at a supply voltage of 0.6 V. The active area is 1.6 mm^2 there are about 1,230 FETs. A new DC/DC level converter has been developed for use in high-speed, low-power storage circuits such as SRAMs and register files. The level converter can increase the DC voltage, which is supplied to an active-load circuit on request, or supply a minimal DC voltage to a load circuit in the stand-by mode. The power dissipation (P) of the 32-word register file with on-chip DC/DC level converters is 459 mW, a reduction to 25.2% of that of an equivalent conventional register file, while the operating frequency (f_c) was 5.17GHz that is 74.8% of f_c for the conventional register file. P for the 512-bit cache SRAM with the new DC/DC level converters is 34.3 mW, 89.7% of the value for an equivalent conventional cache SRAM, with the read-access time of 455 psec, only 1.1% longer than that of the conventional cache SRAM.

• 社団法人電子情報通信学会の論文
• 2002-02-01

著者

• Enomoto Tadayoshi

  Chuo Univ. Tokyo Jpn

関連論文

• A Low Dynamic Power 90-nm CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling Scheme and Fast Motion Estimation Algorithm Called Adaptively Assigned Breaking-off Condition Search(International Workshop on Advanced Image Tec
• Low-Voltage, Low-Power, High-Speed 0.25-μm GaAs HEMT Delay Flip-Flops
• Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
• Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit
• Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array
• Designs of Building Blocks for High-Speed, Low-Power Processors(Special Issue on High-Performance and Low-Power Microprocessors)
• FOREWORD (Special Issue on Low-Power LSI Technologies)

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