On the Complexity of Fault Testing for Reversible Circuits
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概要
- 論文の詳細を見る
This paper shows that it is NP-hard to generate a minimum complete test set for stuck-at faults on a set of wires of a reversible circuit.
- 社団法人電子情報通信学会の論文
- 2005-11-03
著者
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TAYU Satoshi
Department of Communication and Integrated Systems, Tokyo Institute of Technology
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UENO Shuichi
Department of Communication and Integrated Systems, Tokyo Institute of Technology
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Ito Shigeru
Department of Materials and Life Sciences, Faculty of Science and Technology, Sophia University
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Ueno Shuichi
Dept. Of Communications And Integrated Systems Tokyo Institute Of Technology
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Ueno Shuichi
東工大
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Ito Yusuke
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
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Ito Yusuke
Department Of Anesthesiology Toyama Medical And Pharmaceutical University
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Tayu Satoshi
Dept. Of Communications And Integrated Systems Tokyo Institute Of Technology
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Ueno Shuichi
Department Of Communication And Integrated Systems Tokyo Institute Of Technology
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Tayu Satoshi
Department Of Communication And Integrated Systems Tokyo Institute Of Technology
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Ito Shigeru
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
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Ueno Shuichi
Department Of Biological Science Faculty Of Science Yamaguchi University
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Ito Yusuke
Department Of Anesthesiology Tokyo Medical And Dental University Graduate School Of Medicine
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