A Linear Time Algorithm for Constructing Proper-Path-Decomposition of Width Two
スポンサーリンク
概要
- 論文の詳細を見る
The problem of constructing the proper-path-decomposition of width at most 2 has an application to the efficient graph layout into ladders. In this paper, we give a linear time algorithm which, for a given graph with maximum vertex degree at most 3, determines whether the proper-pathwidth of the graph is at most 2, and if so, constructs a proper-path-decomposition of width at most 2.
- 社団法人電子情報通信学会の論文
- 1998-05-25
著者
-
Ueno S
Department Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Ueno Shuichi
Dept. Of Communications And Integrated Systems Tokyo Institute Of Technology
-
Matsubayashi Akira
Faculty Of Engineering Kanazawa University
-
Matsubayashi Akira
The Faculty Of Engineering Utsunomiya University
-
Matsubayashi Akira
Faculty Of Engineering Tokyo Institute Of Technology
-
UENO Shuichi
the Faculty of Engineering, Tokyo Institute of Technology
-
Ueno Shuichi
The Faculty Of Engineering Tokyo Institute Of Technology
関連論文
- A Note on Two Problems of Nano-PLA Design
- A Note on Two Problems of Nano-PLA Design
- A Note on Two Problems of Nano-PLA Design
- A-1-28 A Note on a Problem of Nano-PLA Design
- On the Complexity of Fault Testing for Reversible Circuits
- A-1-26 On the Complexity of Fault Testing for Reversible Circuits
- A-1-8 Bandwidth of Convex Bipartite Graphs
- A-1-8 Characterizations of Two-Directional Orthogonal Ray Graphs
- Orthogonal ray graphs and nano-PLA design (コンカレント工学)
- Orthogonal ray graphs and nano-PLA design (回路とシステム)
- On orthogonal ray graphs (アルゴリズム)
- On Orthogonal Ray Graphs with Applications to NanoPLA Design : Extended Abstract
- On Orthogonal Ray Graphs with Applications to NanoPLA Design : Extended Abstract
- On Orthogonal Ray Graphs with Applications to NanoPLA Design : Extended Abstract
- On the permutation routing in all-optical caterpillar networks (回路とシステム)
- On the permutation routing in all-optical caterpillar networks (コンカレント工学)
- On the Complexity of Embedding of Graphs into Grids with Minimum Congestion (Special Section on Discrete Mathematics and Its Applications)
- A Note on the Complexity of Scheduling for Precedence Constrained Messages in Distributed Systems(Algorithms and Data Structures)
- VLSI Layout of Trees into Grids of Minimum Width
- On the Three-Dimensional Orthogonal Drawing of Series-Parallel Graphs
- A-1-27 On the Three-Dimensional Layout of Butterfly Networks
- On the Orthogonal Drawing of Outerplanar Graphs(Graphs and Networks)
- A-1-31 A Note on Sparse Networks Tolerating Random Faults for Cycles(A-1. 回路とシステム, 基礎・境界)
- On the Orthogonal Drawing of Series-Parallel Graphs
- On the Three-Dimensional Channel Routing
- Genetic polymorphisms of serotonin and dopamine transporters in mental disorders
- Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two
- Universal Graphs for Graphs with Bounded Path-Width
- On the Proper-Path-Decomposition of Trees
- A Linear Time Algorithm for Constructing Proper-Path-Decomposition of Width Two
- A-1-25 On Efficient Universal Quantum Circuits
- Universal test sets for reversible circuits (コンカレント工学)
- Universal test sets for reversible circuits (回路とシステム)
- A-1-14 Fault Testing for Linear Reversible Circuits
- On Fault Testing for Reversible Circuits
- On the fault testing for reversible circuits (アルゴリズム)
- The Complexity of Embedding of Acyclic Graphs into Grids with Minimum Congestion
- A Note on the Circuit-switched Fixed Routing in Networks (特集 並列処理)
- A Note on the Implementation of de Bruijn Networks by the Optical Transpose Interconnection System(Graphs and Networks)
- On Two Problems of Nano-PLA Design
- A-1-7 Universal Test Sets for Reversible Circuits
- AS-1-1 The Complexity of Fault Testing for Reversible Circuits
- On the Complexity of Minimum Congestion Embedding of Acyclic Graphs into Ladders
- Minimum Congestion Embedding of Complete Binary Trees into Tori
- On the Complexity of Energy-Aware Mapping for NoCs (信号処理)
- On the Complexity of Energy-Aware Mapping for NoCs (回路とシステム)
- On the Complexity of Energy-Aware Mapping for NoCs (通信方式)
- On Minimum Feedback Vertex Sets in Graphs (システム数理と応用)
- On Minimum Feedback Vertex Sets in Graphs (信号処理)
- On Minimum Feedback Vertex Sets in Graphs (VLSI設計技術)
- On Minimum Feedback Vertex Sets in Graphs (回路とシステム)
- A-1-35 Minimum Feedback Vertex Sets in Permutation Bigraphs
- On Efficient Universal Quantum Circuits (回路とシステム)
- On Efficient Universal Quantum Circuits (システム数理と応用)