HTS Surface-Modified Junctions with Integrated Ground-Planes for SFQ Circuits(<特集>Special Issue on Superconductive Electronics)
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概要
- 論文の詳細を見る
We fabricated ramp-edge junctions with barriers by modifying surface and integrating ground-planes. The fabricated junctions had current-voltage characteristics consistent with the resistive shunted-junction model. We also obtained a 1-sigma spread in the critical current of 7.9% for 100 junctions at 4.2 K. The ground-plane reduced the sheet inductance of a stripline by a factor of 3. The quality of the ground-plane was improved by using an anneal in oxygen atmosphere after fabrication. The sheet inductance of a counter-electrode with a ground-plane was 1.0 pH per square at 4.2 K.
- 社団法人電子情報通信学会の論文
- 2002-03-01
著者
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TSUKAMOTO Akira
Advanced Research Laboratory, Hitachi, Ltd.
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TAKAGI Kazumasa
Advanced Research Laboratory, Hitachi, Ltd.
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Tsukamoto Akira
Advanced Research Laboratory Hitachi Ltd.
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Takagi K
Advanced Research Laboratory Hitachi Ltd.
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Takagi Kazumasa
Advanced Research Laboratory Hitachi Ltd.
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Tsukamoto A
Advanced Research Laboratory Hitachi Ltd.
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SAITOH Kazuo
Advanced Research Laboratory, Hitachi, Ltd.
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Saitoh K
Institute Of Physics University Of Tsukuba
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Saitoh Kazuo
Advanced Research Laboratory Hitachi Ltd.
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Saitoh K
Hitachi Ltd. Kokubunji‐shi Jpn
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SOUTOME Yoshihisa
Advanced Research Laboratory, Hitachi Ltd.
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FUKAZAWA Tokuumi
Advanced Research Laboratory, Hitachi Ltd.
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Soutome Y
Advanced Research Laboratory Hitachi Ltd.
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Fukazawa T
Advanced Research Laboratory Hitachi Ltd.
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