Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits(Scan Testing)(<Special Section>Test and Verification of VLSI)

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概要

• 論文の詳細を見る

• The partially rotational scan (PRS) technique greatly reduces the amount of data needed for n-detection testing. It also enables at-speed testing using low-speed testers. We designed tester intellectual properties (tester IP) with PRS for Viper and COMET II processors. When PRS was applied to a Viper processor, we obtained test data that provided the same fault coverage as with a set of automatic test pattern generation (ATPG) test vectors, although the amount of test data was 16% that of the ATPG. When the PRS technique was applied to a COMET II processor with full-scan design, we obtained test data that provided the same fault coverage as with a set of ATPG test vectors, although the amount of test data was 10% that of the ATPG. We also estimated hardware overhead and testtime.

• 社団法人電子情報通信学会の論文
• 2004-03-01

著者

• ARAI Masayuki

  Tokyo Metropolitan University

• IWASAKI Kazuhiko

  Tokyo Metropolitan University

• Fukumoto Satoshi

  Tokyo Metropolitan Univ. Hachioji‐shi Jpn

• Iwasaki K

  Tokyo Metropolitan Univ. Tokyo Jpn

• Iwasaki Kazuhiko

  Faculty Of System Design Tokyo Metropolitan University

• Arai Masayuki

  Tokyo Metropolitan Univ. Tokyo Jpn

• ICHINO Kenichi

  Tokyo Metropolitan University

• WATANABE Ko-ichi

  Tokyo Metropolitan University

• Watanabe K

  Tokyo Metropolitan University

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