Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression
スポンサーリンク
概要
- 論文の詳細を見る
This paper describes a simple means to enable direct diagnosis by bypassing MISRs on a small set of tests (MISR-bypass test mode) while achieving ultimate output compression using MISRs for the majority of tests (MISR-enabled test mode.) By combining two compression schemes, XOR and MISRs in the same device, it becomes possible to have high compression and still support compression mode volume diagnostics. In our experiment, the MISR-bypass test was first executed and at 10% of the total test set the MISR-enabled test was performed. The results show that compared with MISR+XOR-based compression the proposed technique provides better volume diagnosis with slightly small (0.71X to 0.97X) compaction ratio. The scan cycles are about the same as the MISR-enabled mode. A possible application to partial good chips is also shown.
著者
-
UZZAMAN Anis
Cadence Design Systems, Inc.
-
KELLER Brion
Cadence Design Systems, Inc.
-
FOUTZ Brian
Cadence Design Systems, Inc.
-
BHATIA Sandeep
Cadence Design Systems, Inc.
-
BARTENSTEIN Thomas
Cadence Design Systems, Inc.
-
ARAI Masayuki
Tokyo Metropolitan University
-
IWASAKI Kazuhiko
Tokyo Metropolitan University
-
Keller Brion
Cadence Design Systems Inc.
関連論文
- Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression
- Note on programmable on-product clock generation (OPCG) circuitry for low power aware delay test (ディペンダブルコンピューティング)
- Analytical Model on Hybrid State Saving with a Limited Number of Checkpoints and Bound Rollbacks(Reliability, Maintainability and Safety Analysis)
- Reliability Analysis of a Convolutional-Code-Based Packet Level FEC under Limited Buffer Size(Reliability, Maintainability and Safety Analysis)
- Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits(Scan Testing)(Test and Verification of VLSI)
- Seed Selection Procedure for LFSR-Based Random Pattern Generators(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
- High-Assurance Video Conference System over the Internet(Network Systems and Applications)(Assurance Systems and Networks)
- A Technique for Constructing Dependable Internet Server Cluster(Fault Tolerance)
- C-24 Implementation and Experiments on Dependable Video Conference System
- Fault-Tolerance Design for Muiticast Using Convolutional-Code-Based FEC and Its Analytical Evaluation
- Analytical Evaluation of Internet Packet Loss Recovery Using Convolutional Codes
- Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan(Special Issue on Test and Verification of VLSI)
- Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression
- Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
- Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
- Study on Expansion of Convolutional Compactors over Galois Field
- Analysis of Probabilistic Trapezoid Protocol for Data Replication