Note on programmable on-product clock generation (OPCG) circuitry for low power aware delay test (ディペンダブルコンピューティング)

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概要

• 論文の詳細を見る

• This paper describes how we provide a mean for dealing with the programmable aspects of on-product clock generation(OPCG)for use during ATPG and how that can also help with low power delay test. The system described in this paper automatically generates mode initialization sequence, setup sequence, test sequence and others and enables low power aware delay test when faster on product clocks are present on board. This system has successfully been used to process delay test for ASIC chips even with 22 PLLs on board.

• 社団法人電子情報通信学会の論文
• 2009-12-04

著者

• UZZAMAN Anis

  Cadence Design Systems, Inc.

• KELLER Brion

  Cadence Design Systems, Inc.

• ARAI Masayuki

  Tokyo Metropolitan University

• IWASAKI Kazuhiko

  Tokyo Metropolitan University

• Keller Brion

  Cadence Design Systems Inc.

• Iwasaki K

  Tokyo Metropolitan Univ. Tokyo Jpn

• Iwasaki Kazuhiko

  Faculty Of System Design Tokyo Metropolitan University

• Iwasaki Kazuhiko

  Faculty Of Engineering Chiba University

• Arai Masayuki

  Tokyo Metropolitan Univ. Tokyo Jpn

• Uzzaman Anis

  Cadence Design Systems Inc.:faculty Of System Design Tokyo Metropolitan University

• Snethen Tom

  Cadence Design Systems Inc.

• Arai Masayuki

  Faculty of System Design, Tokyo Metropolitan University

• Uzzaman Anis

  Cadence Design Systems Inc.

• Arai Masayuki

  Faculty Of System Design Tokyo Metropolitan University

関連論文

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• Note on programmable on-product clock generation (OPCG) circuitry for low power aware delay test (ディペンダブルコンピューティング)
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