Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
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概要
- 論文の詳細を見る
In this paper, we propose a scheme for test data reduction which uses broadcaster along with bit-flipping circuit. The proposed scheme can reduce test data without degrading the fault coverage of ATPG, and without requiring or modifying the arrangement of CUT. We theoretically analyze the test data size by the proposed scheme. The numerical examples obtained by the analysis and experimental results show that our scheme can effectively reduce test data if the care-bit rate is not so much low according to the number of scan chains. We also discuss the hybrid scheme of random-pattern-based flipping and single-input-based flipping.
- （社）電子情報通信学会の論文
- 2008-03-01
著者
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ARAI Masayuki
Tokyo Metropolitan University
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IWASAKI Kazuhiko
Tokyo Metropolitan University
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Fukumoto Satoshi
Tokyo Metropolitan Univ. Hachioji‐shi Jpn
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Iwasaki K
Tokyo Metropolitan Univ. Tokyo Jpn
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Iwasaki Kazuhiko
Faculty Of System Design Tokyo Metropolitan University
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Iwasaki Kazuhiko
Faculty Of Engineering Chiba University
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Arai Masayuki
Tokyo Metropolitan Univ. Tokyo Jpn
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Arai Masayuki
Faculty of System Design, Tokyo Metropolitan University
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FUKUMOTO Satoshi
Faculty of System Design, Tokyo Metropolitan University
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Arai Masayuki
Faculty Of System Design Tokyo Metropolitan University
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