Sparse Realization of Passive Reduced-Order Interconnect Models via PRIMA (VLSI Design Technology and CAD)
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概要
- 論文の詳細を見る
This paper describes a sparse realization of passive reduced-order interconnect models via PRIMA to provide the SPICE compatible models. It is demonstrated that, if the SPICE models are directly realized so that the reduced-order equations obtained via PRIMA are stamped into the MNA matrix, the simulations of networks containing the macromodels become computationally inefficient when size of the reduced-order equations is relatively large. This is due to dense coefficient matrices of the reduced-order equations resulting from congruent transformations in PRIMA. To overcome this disadvantage, we propose a sparse realization of the reduced-order models. Since the expression is equivalent to the reduced-order equations, the passivity of the SPICE models generated is also guaranteed. Computational efficiency on SPICE is demonstrated in performing the transient analysis of circuits containing the proposed macromodels.
- 社団法人電子情報通信学会の論文
- 2004-01-01
著者
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TANAKA Mamoru
Department of Electrical and Electronics Engineering, Sophia University
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TANJI Yuichi
Department of Reliability-based Information Systems Engineering, Kagawa University
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Tanji Yuichi
Department Of Reliability-based Information Systems Engineering Kagawa University
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MATSUMOTO Yuya
Department of Electricaland Electronics Engineering, Sophia University
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Matsumoto Yuya
Department Of Electricaland Electronics Engineering Sophia University
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Tanaka Mamoru
Department Of Electrical And Electronics Engineering Sophia University
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Tanaka Mamoru
Department Of Applied Chemistry Kobe City College Of Technology
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Tanaka Mamoru
Department Of Electricaland Electronics Engineering Sophia University
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