Hierarchical Least-Squares Algorithm for Macromodeling High-Speed Interconnects Characterized by Sampled Data

概要

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The interconnect analysis of on- and off-chips is very important in the design of high-speed signal processing, digital communication, and microwave electronic systems. When the interconnects are characterized by sampled data via electromagnetic analysis, the circuit-level simulation of the network requires rational approximation of the sampled data. Since the frequency band of the sampled data is more than 10 GHz, the rational function must fit into it at many frequency points. The rational function is approximated using the orthogonal least-squares method. With an increase in the number of the fitting data, the least-squares method suffers from a singularity problem. To avoid this, the sampled data are hierarchically approximated in this paper. Moreover, to reduce the computational cost of the circuit-level simulation, the parameter matrix of the interconnects is approximated by a rational matrix with one common denominator polynomial, and the selective orthogonalization procedure is presented.
社団法人電子情報通信学会の論文
2000-09-25