CLASSIC:An O(n^2)-Heuristic Algorithm for Microcode Bit Optimization Based on Incompleteness Relations

スポンサーリンク

概要

• 論文の詳細を見る

• This paper presents a heuristic algorithm called CLASSIC for the minimization of the control memory width in microprogrammed processors or the instruction memory width of application-specific VLIW(Very Long Instruction Word)processors. CLASSIC results in nearly optimal solutions with the time complexity of O(n^2), where n denotes the number of microoperations. In this paper, we also propose the so-called incompleteness relations which are exploited for the minimization of the control memory width. Experiments using various examples have shown that CLASSIC always achieves smaller microprogram widths compared to the earlier techniques based on the maximal compatibility class or the minimal AND/OR set. The results show that CLASSIC can reduce the control memory width by 34.2% on average compared with a heuristic compatibility class algorithm.

• 社団法人電子情報通信学会の論文
• 2000-05-25

著者

• PARK In-Cheol

  Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and T

• Park In-cheol

  Department Of Eecs Kaist

• Choi Young-doo

  Department Of Electrical Engineering Korea Advanced Institute Of Science And Technology:(present Add

• KYUNG Chong-Min

  Department of Electrical Engineering, Korea Advanced Institute of Science and Technology

• Kyung Chong-min

  Department Of Eecs Kaist Taejon

関連論文

• An Area-Efficient and Fully Synthesizable Bluetooth Baseband Module for Wireless Communication(Integrated Electronics)
• Improving Dictionary-Based Code Compression in VLIW Architectures (Special Section on VLSI Design and CAD Algorithms)
• Parallel Decoding of Context-Based Adaptive Binary Arithmetic Codes Based on Most Probable Symbol Prediction(Image Processing and Video Processing)
• Loop and Address Code Optimization for Digital Signal Processors
• A Hierarchical Circuit Clustering Algorithm with Stable Performance
• CLASSIC:An O(n^2)-Heuristic Algorithm for Microcode Bit Optimization Based on Incompleteness Relations
• Issues on the Interface Synthesis between Intellectual Properties Operating at Different Clock Frequencies
• A New Single-Clock Flip-Flop for Half-Swing Clocking (Special Section on VLSI Design and CAD Algorithms)
• Path-Classified Trace Cache for Improving Hit Ratio in Wide-Issue Processors
• SEWD:A Cache Architecture to Speed up the Misaligned Instruction Prefetch
• An Efficient Routing Algorithm for Symmetrical FPGAs Using Reliable Cost Metrics(VLSI Design Technology and CAD)(Regular Section)
• A Supplementary Scheme for Reducing Cache Access Time

もっと見る 閉じる

スポンサーリンク