Improving Dictionary-Based Code Compression in VLIW Architectures (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
Reducing code size is crucial in embedded systems as well as in high-performance systems to overcome the communication bottleneck between memory and CPU, especially with VLIW (Very Long Instruction Word) processors that require a high-bandwidth instruction prefetching. This paper presents a new approach for dictionary-based code compression in VLIW processor-based systems using isomorphism among instruction words. After we divide instruction words into two groups, one for opcode group and the other for operand group, the proposed compression algorithm is applied to each group for maximal code compression. Frequently-used instruction words are extracted from the original code to be mapped into two dictionaries, an opcode dictionary and an operand dictionary. According to the SPEC95 benchmarks, the proposed technique has achieved an average code compression ratio of 63%, 69%, and 71% in a 4-issue, 8-issue, and 12-issue VLIW architecture, respectively.
- 社団法人電子情報通信学会の論文
- 1999-11-25
著者
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PARK In-Cheol
Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and T
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Park I‐c
Kaist
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Nam S‐j
Department Of Electrical Engineering Korea Advanced Institute Of Science And Technology
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Park In-cheol
Department Of Eecs Kaist
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NAM Sang-Joon
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology
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KYUNG Chong-Min
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology
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Kyung Chong-min
Department Of Eecs Kaist Taejon
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