Loop and Address Code Optimization for Digital Signal Processors
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概要
- 論文の詳細を見る
This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to loops and the address computation of array accesses. The information is used in generating hardware loop instructions and parallel instructions provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to make it easy to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance.
- 社団法人電子情報通信学会の論文
- 2002-06-01
著者
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PARK In-Cheol
Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and T
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Park In-cheol
Department Of Eecs Kaist
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Lee Jong-yeol
Department Of Eecs Kaist
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