A New Single-Clock Flip-Flop for Half-Swing Clocking (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
A new flip-flop configuration for half-swing clocking is proposed to save total clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or any additional logics which were used in the earlier half-swing clocking schemes. V_<cc> is supplied to the random logic circuits and flip-flops while V_<cc>/2 is supplied to the clock network and some parts of the flip-flop to reduce the power consumed in the clock network. Compared to the conventional scheme, the proposed flip-flop configuration can save the clocking power by 40%.
- 社団法人電子情報通信学会の論文
- 1999-11-25
著者
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Park In-cheol
Department Of Electrical Engineering Korea Advanced Institute Of Science And Technology
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Park In-cheol
Department Of Eecs Kaist
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Kyung Chong-min
Department Of Eecs Kaist Taejon
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KWON Young-Su
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology
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Kwon Young-su
Department Of Electrical Engineering Korea Advanced Institute Of Science And Technology
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