Simulation of sub-0.1 μm T-gate Trilayer Process in HEMTs for Millimeter-wave Frequencies Using 50-kV and 100-kV Electron Beam Lithography System (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))

概要

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A computationally efficient and accurate Monte Carlo (MC) simulator of electron beam lithography process has been developed for sub-0.1 μm T-shaped gate formation in the HEMT devices for the millimeter-wave frequencies. For the exposure process by electron beam, we newly and efficiently modeled the inner-shell electron scattering and its energy loss with an incident electron for multi-layer resists and heterogeneous multi-layer substrates in the MC simulation. In the T-gate formation, we usually use the different developer for each resist layer in order to obtain good reproducibility in the fabrication of PHEMT devices. To model accurately the real fabrication process of electron beam lithography, we have applied the different developers for three-layer resist system. Our simulation results have been verified by comparing with the SEM experiments. By using this model, we simulated the sub-0.1 μm T-gate fabrication process in the HEMT device using 100-kV electron beam lithography exposure system. In this work, we show and discuss the difference between 50-kV and 100-kV electron beam lithography exposure pattering shape for the sub-0.1 μm trilayer T-gate formation process.
社団法人電子情報通信学会の論文
2003-06-23