FFT多倍長乗算器のVLSI設計(科学技術計算と数値解析(多倍長科学技術計算の基礎と応用), <特集>平成17年研究部会連合発表会)

概要

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We designed a VLSI (Very Large Scale Integrated circuit) chip of FFT multiplier using a floating-point representation with optimal data length based on an experimental error analysis. Using the hardware implementation, we can perform 2^5 to 2^<13> hexadecimal digit (39 to 9,831 decimal digit) multiplication 25.1 to 45.6 times (33.9 times in average) faster than using FFTW3, at an area cost of 9.05mm^2. The hardware FFT multiplier has 64 times faster performance than exflib (a multi-digit arithmetic library using Karatsuba method) for longer than 2^<21> hexadecimal digit (≒2,520,000 decimal digit) multiplication. Considering the wide applications of its FFT modules, the performance and cost of the FFT multiplier justifies the VLSI implementation.
日本応用数理学会の論文
2005-09-25