A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology

スポンサーリンク

概要

• 論文の詳細を見る

• The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple on-off keying (OOK) modulation is adopted for low power consumption. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumption of the transmitter and receiver are 19.2mA and 48.2mA respectively. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.

• 2012-07-01

著者

• Fujimoto Ryuichi

  Toshiba Corp. Kawasaki‐shi Jpn

• Yodprasit Uroschanit

  Graduate School Of Advanced Sciences Of Matter Hiroshima University

• Takano Kyoya

  Graduate School Of Engineering The University Of Tokyo

• Fujishima Minoru

  Graduate School Of Advanced Sciences Of Matter Hiroshima University

• MOTOYOSHI Mizuki

  Graduate School of Advanced Sciences of Matter, Hiroshima University

• FUJIMOTO Ryuichi

  Toshiba Corporation, Semiconductor and Storage Products Company

• FUJIMOTO Ryuichi

  Toshiba

• TAKANO Kyoya

  Graduate School of Advanced Sciences of Matter, Hiroshima University

関連論文

• 1.9 GHz Si Direct Conversion Receiver IC for QPSK Modulation Systems (Special Issue on Microwave Devices for Mobile Communications)
• Device Modeling Techniques for High-Frequency Circuits Design Using Bond-Based Design at over 100GHz
• 140GHz CMOS amplifier with group delay variation of 10.2ps and 0.1dB bandwidth of 12GHz
• Large-Scale Emulation of Quantum Computing Based on Nonzero State Transitions
• Analysis of De-Embedding Error Cancellation in Cascade Circuit Design
• A -104dBc/Hz In-Band Phase Noise 3GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter
• New Performance Indicators of Metal--Oxide--Semiconductor Field-Effect Transistors for High-Frequency Power-Conscious Design
• Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit
• A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology
• A-104dBc/Hz In-Band Phase Noise 3GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter
• A -70dBm-Sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX Transceiver for TransferJet™ SoC in 65nm CMOS
• 135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset
• A 120GHz/140GHz Dual-Channel OOK Receiver Using 65nm CMOS Technology
• C-2-37 Design for Maximum FOM of 79GHz Power Amplifier with Temperature Compensation

もっと見る 閉じる

スポンサーリンク