Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit
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概要
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In this paper, we propose a new method for the bias-dependent parameter extraction of a MOSFET, which covers DC to over 100GHz. The DC MOSFET model provided by the chip foundry is assumed to be correct, and the core DC characteristics are designed to be asymptotically recovered at low frequencies. This is carried out by representing the corrections required at high frequencies using a bias-dependent Y matrix, assuming that a parasitic nonlinear two-port matrix (Y-wrapper) is connected in parallel with the core MOSFET. The Y-wrapper can also handle the nonreciprocity of the parasitic components, that is, the asymmetry of the Y matrix. The reliability of the Y-wrapper model is confirmed through the simulation and measurement of a one-stage common-source amplifier operating at several bias points. This paper will not discuss about non-linearity.
- 2012-06-01
著者
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Fujimoto Ryuichi
Toshiba Corp. Kawasaki‐shi Jpn
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Takano Kyoya
Graduate School Of Engineering The University Of Tokyo
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Fujishima Minoru
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Katayama Kosuke
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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MOTOYOSHI Mizuki
Graduate School of Advanced Sciences of Matter, Hiroshima University
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FUJIMOTO Ryuichi
Toshiba Corporation, Semiconductor Company
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FUJIMOTO Ryuichi
Toshiba
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TAKANO Kyoya
Graduate School of Advanced Sciences of Matter, Hiroshima University
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