135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset
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概要
- 論文の詳細を見る
An amplitude shift keying transmitter and receiver chipset with low power consumption using 40nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region.
著者
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Ono Naoko
Toshiba Corporation
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Fujishima Minoru
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Katayama Kosuke
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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MOTOYOSHI Mizuki
Graduate School of Advanced Sciences of Matter, Hiroshima University
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TAKANO Kyoya
Graduate School of Advanced Sciences of Matter, Hiroshima University
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