A High Efficiency, Extended Load Range Boost Regulator Optimized for Energy Harvesting Applications
スポンサーリンク
概要
- 論文の詳細を見る
- 2012-03-29
著者
-
Matsuda Jun-ichi
Toko Inc.
-
Kobayashi Haruo
Gunma Univ. Kiryu‐shi Jpn
-
Takai Nobukazu
Gunma Univ. Kiryu‐shi Jpn
-
Niitsu Kiichi
Gunma University
-
Kobayashi Haruo
Gunma University
-
Niitsu Kiichi
Department Of Electronic Engineering Graduate School Of Engineering Gunma University
-
Nemoto Kenji
Akm Technology Corporation
-
Matsuda Jun-ichi
Asahi Kasei Power Devices Corporation
-
NOSKER Zachary
Gunma University
-
KOBORI Yasunori
Gunma University
-
OOMORI Takeshi
AKM Technology Corporation
-
ODAGUCHI Takahiro
AKM Technology Corporation
-
NAKANISHI Isao
AKM Technology Corporation
-
Takai Nobukazu
Gunma University
関連論文
- Noise-Coupled ΔΣAD Modulator with Shared OP-Amp
- EMI Reduction by Spread-Spectrum Clocking in Digitally-Controlled DC-DC Converters
- Analysis of Coupled Inductors for Low-Ripple Fast-Response Buck Converter
- SAR ADC Algorithm with Redundancy and Digital Error Correction
- A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm(Analog Circuits and Related SoC Integration Technologies)
- Complex Bandpass ΔΣAD Modulator Architecture without I, Q-Path Crossing Layout(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Novel Architecture of Feedforward Second-Order Multibit ΔΣAD Modulator
- THD Measurement and Compensation for Analog Circuits with Fine CMOS Devices
- High-Speed Continuous-Time Subsampling Bandpass ΔΣAD Modulator Architecture Employing Radio Frequency DAC(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Highly-Efficient Low-Voltage-0peration Charge Pump Circuits Using Bootstrapped Gate Transfer Switches (特集 低電圧・低消費電力化アナログ回路技術)
- C-12-48 Finite Aperture Time and Sampling Bandwidth
- Production Test Considerations for Mixed-signal IC with Background Calibration
- SAR ADC Architecture with Digital Error Correction
- Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths(AD/DA, Analog Circuit and Device Technologies)
- Rail-to-Rail OTA Utilizing Linear V-I Conversion Circuit Whose Input Stage is Composed of Single Channel MOSFETs(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme
- Design for Testability That Reduces Linearity Testing Time of SAR ADCs
- A 33% Improvement in Efficiency of Wireless Inter-Chip Power Delivery by Thin Film Magnetic Material for Three-Dimensional System Integration
- Finite Aperture Time Effects in Sampling Circuit (AD/DA, PLL)
- A High Efficiency, Extended Load Range Boost Regulator Optimized for Energy Harvesting Applications
- Design Methodology for Determining the Number of Stages in a Cascaded Time Amplifier to Minimize Area Consumption
- Two-Tone Signal Generation for ADC Testing
- A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines