Design Methodology for Determining the Number of Stages in a Cascaded Time Amplifier to Minimize Area Consumption

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概要

• 論文の詳細を見る

• This paper describes a design methodology for determining the number of stages in a cascaded time amplifier to minimize the area consumption. The total area consumption is categorized into three parts, which allows mathematical analysis and optimization to be performed. A combination of the proposed mathematical analysis and 2D mapping can determine the number of stages to minimize the area consumption.

著者

• Niitsu Kiichi

  Department Of Electronic Engineering Graduate School Of Engineering Gunma University

• KOBAYASHI Haruo

  Division of Electronics and Informatics, Faculty of Science and Technology, Gunma University

• Harigai Naohiro

  Division of Electronics and Informatics, Faculty of Science and Technology, Gunma University

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