Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems
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概要
- 論文の詳細を見る
This paper presents a low complexity partially folded architecture of transposed FIR filter and cubic B-spline interpolator for ATSC terrestrial broadcasting systems. By using the multiplexer, the proposed FIR filter and interpolator can provide high clock frequency and low hardware complexity. A binary representation method was used for designing the high order FIR filter. Also, in order to compensate the truncation error of FIR filter outputs, a fixed-point range detection method was used. The proposed partially folded architecture was designed and implemented with 90-nm CMOS technology that had a supply voltage of 1.1V. The implementation results show that the proposed architectures have 12% and 16% less hardware complexity than the other kinds of architecture. Also, both the filter and the interpolator operate at a clock frequency of 200MHz and 385MHz, respectively.
- 2011-03-01
著者
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Choi Chang-seok
School Of Information And Communication Engineering Inha University
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Lee Hanho
School Of Information And Communication Engineering Inha University
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KIM Yong-Kyu
School of Information and Communication Engineering, Inha University
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Kim Yong-kyu
School Of Information And Communication Engineering Inha University
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Lee Hanho
School Of Information And Communication Engineering Inha Univ.
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