A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders
スポンサーリンク
概要
- 論文の詳細を見る
This paper presents a novel high-speed low-complexity pipelined degree-computationless modified Euclidean (pDCME) algorithm architecture for high-speed RS decoders. The pDCME algorithm allows elimination of the degree-computation so as to reduce hardware complexity and obtain high-speed processing. A high-speed RS decoder based on the pDCME algorithm has been designed and implemented with 0.13-μm CMOS standard cell technology in a supply voltage of 1.1V. The proposed RS decoder operates at a clock frequency of 660MHz and has a throughput of 5.3Gb/s. The proposed architecture requires approximately 15% fewer gate counts and a simpler control logic than architectures based on the popular modified Euclidean algorithm.
- 2008-03-01
著者
-
Lee Seungbeom
School Of Information And Communication Engineering Inha University
-
Lee Hanho
School Of Information And Communication Engineering Inha University
-
Lee Hanho
School Of Information And Communication Engineering Inha Univ.
関連論文
- A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform(Reconfigurable System and Applications,Reconfigurable Systems)
- A Design and Performance of 4-Parallel MB-OFDM UWB Receiver(Wireless Communication Technologies)
- A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders
- Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems
- High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications
- A High-Speed Two-Parallel Radix-2^4 FFT/IFFT Processor for MB-OFDM UWB Systems
- Power-Aware Scalable Pipelined Booth Multiplier(VLSI Design Technology and CAD)
- High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems
- Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications