Power-Aware Scalable Pipelined Booth Multiplier(VLSI Design Technology and CAD)

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概要

• 論文の詳細を見る

• An energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this letter presents a low-power power-aware scalable pipelined Booth multiplier that makes use of dynamic-range detection unit, sharing common functional units, ensemble of optimized Wallace-trees and a 4-bit array-based adder-tree for DSP applications.

• 社団法人電子情報通信学会の論文
• 2005-11-01

著者

• Lee Hanho

  School Of Information And Communication Engineering Inha University

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