A High-Speed Two-Parallel Radix-2^4 FFT/IFFT Processor for MB-OFDM UWB Systems
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概要
- 論文の詳細を見る
This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-24 FFT/IFFT processor for MB-OFDM ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using a two-parallel data-path scheme and a single-path delay-feedback (SDF) structure. The radix-24 FFT algorithm is also realized in our processor to reduce the number of complex multiplications. The proposed FFT/IFFT processor has been designed and implemented with 0.18μm CMOS technology in a supply voltage of 1.8V. The proposed two-parallel FFT/IFFT processor has a throughput rate of up to 900Msample/s at 450MHz while requiring much smaller hardware complexity and low power consumption.
- （社）電子情報通信学会の論文
- 2008-04-01
著者
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Lee Hanho
School Of Information And Communication Engineering Inha University
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LEE Jeesung
School of Information and Communication Engineering, Inha University
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Lee Jeesung
School Of Information And Communication Engineering Inha University
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Lee Hanho
School Of Information And Communication Engineering Inha Univ.
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