Simplified 20-μm Pitch Vertical Interconnection Process for 3D Chip Stacking
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概要
- 論文の詳細を見る
- 2009-05-01
著者
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Mizuno Jun
Nanotechnology Research Laboratory, Waseda University
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SAKUMA Katsuyuki
Department of Machine Intelligence and Systems Engineering, Tohoku University
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Shoji Shuichi
School Of Fundamental Science And Engineering Waseda University
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Shoji Shuichi
Department Of Science And Engineering Waseda University
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Mizuno Jun
Nanotechnology Research Laboratory Waseda University
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Mizuno Jun
Department Of Science And Engineering Waseda University
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Shoji Shuichi
Department Of Electrical Engineering And Bioscience Waseda University
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NAGAI Noriyasu
Department of Science and Engineering, Waseda University
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SAITO Mikiko
Department of Science and Engineering, Waseda University
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Saito Mikiko
Department Of Science And Engineering Waseda University
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Nagai Noriyasu
Department Of Science And Engineering Waseda University
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Sakuma Katsuyuki
Department Of Science And Engineering Waseda University
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