Study of Stress from Discontinuous SiN Liner for Fully-Silicided Gate Process
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概要
- 論文の詳細を見る
- 2007-09-19
著者
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MIYAGAWA Yoshihiro
Process Technology Development Division, Renesas Technology Corp.
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NISHIDA Yukio
Process Technology Development Division, Renesas Technology Corp.
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YAMASHITA Tomohiro
Process Technology Development Div., Renesas Technology Corp.
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OKAGAKI Takeshi
Process Technology Development Div., Renesas Technology Corp.
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YUGAMI Jiro
Process Technology Development Div., Renesas Technology Corp.
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ODA Hidekazu
Process Technology Development Div., Renesas Technology Corp.
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INOUE Yasuo
Process Technology Development Div., Renesas Technology Corp.
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SHIBAHARA Kentaro
Graduate School of Advanced Sciences of Matter, Hiroshima University
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Yugami Jiro
Process Technology Development Div. Renesas Technology Corp.
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Yugami Jiro
Process Development Dept. Process Technology Development Div. Production And Technology Unit Renesas
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Oda Hidekazu
Process Technology Development Div. Renesas Technology Corp.
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Shibahara Kentaro
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Yamashita Tomohiro
Process Technology Development Div. Renesas Technology Corp.
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Nishida Yukio
Process Technology Development Div. Renesas Technology Corp.
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Okagaki Takeshi
Process Technology Development Div. Renesas Technology Corp.
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Miyagawa Yoshihiro
Process Technology Development Div. Renesas Technology Corp.
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Inoue Yasuo
Process Technology Development Div. Renesas Technology Corp.
関連論文
- Local Bonding Structure of High-Stress Silicon Nitride Film modified by UV Curing for Strained-Silicon Technology beyond 45nm Node SoC Devices
- Study of Stress from Discontinuous SiN Liner for Fully-Silicided Gate Process
- Low temperature divided CVD technique for TiN metal gate electrodes of p-MISFETs
- Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-$k$/Metal Gate Transistor
- High Soft-Error Tolerance Body-Tied Silicon-on-Insulator Technology with Partial Trench Isolation
- Diffusion Control Techniques for TiN Stacked Metal Gate Electrodes for p-Type Metal Insulator Semiconductor Field Effect Transistors
- Layout-Independent Transistor with Stress-Controlled and Highly Manufacturable Shallow Trench Isolation Process
- Effect of NH3-Free Silicon Nitride for Protection Layer of Magnetic Tunnel Junction on Magnetic Properties of Magnetoresistive Random Access Memory
- Effect of N2 Gas Flow Ratio in Plasma-Enhanced Chemical Vapor Deposition with SiH4–NH3–N2–He Gas Mixture on Stress Relaxation of Silicon Nitride
- Stress from Discontinuous SiN Liner for Fully Silicided Gate Process
- Local Bonding Structure of High-Stress Silicon Nitride Film Modified by UV Curing for Strained Silicon Technology beyond 45 nm Node SoC Devices