Stress from Discontinuous SiN Liner for Fully Silicided Gate Process

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概要

• 論文の詳細を見る

• New materials often force modification in a metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process and a device structure. In our investigation, a high-stress silicon nitride (SiN) contact etch stopper layer (CESL), which improves device performance by straining the Si lattice, was used as the modified structure. A portion of its gate surround was cut to fabricate a fully silicided (FUSI) metal gate. FET characteristics of a polycrystalline silicon (poly-Si) gate and a Ni-FUSI gate MOSFET with a discontinuous CESL were compared with those of a poly-Si gate MOSFET with an ordinary continuous CESL for several SiN-stress conditions. It was found that the removal of a gate-top CESL diminishes mobility modulation effects of a high-stress CESL. It was also demonstrated that stress due to a FUSI gate compensates the effect of gate-top CESL removal. Mobility enhancement utilizing a high-stress SiN film was still effective for a FUSI gate process.

• 2008-04-25

著者

• Shibahara Kentaro

  Graduate School Of Advanced Sciences Of Matter Hiroshima University

• Oda Hidekazu

  Production Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Nishida Yukio

  Production Technology Development Division, Renesas Technology Corp., 751, Horiguchi, Hitachinaka, Ibaraki 312-8504, Japan

• Shibahara Kentaro

  Graduate School of Advanced Sciences of Matter, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan

• Inoue Yasuo

  Production Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Yamashita Tomohiro

  Production Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Okagaki Takeshi

  Production Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Miyagawa Yoshihiro

  Production Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Yugami Jiro

  Production Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Nishida Yukio

  Production Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

関連論文

• Study of Stress from Discontinuous SiN Liner for Fully-Silicided Gate Process
• Temperature Coefficient of Threshold Voltage in High-$k$ Metal Gate Transistors with Various TiN and Capping Layer Thicknesses
• Stress from Discontinuous SiN Liner for Fully Silicided Gate Process

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