High Soft-Error Tolerance Body-Tied Silicon-on-Insulator Technology with Partial Trench Isolation

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概要

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• This paper presents soft-error tolerance for partially depleted silicon-on-insulator (SOI) devices with partial trench isolation (PTI) that realize a body-tied structure. Mechanism of charge collections due to alpha-particle strikes is clarified for a body-tied SOI device with the PTI structure and a body-floating SOI device. It is estimated that the soft-error tolerance of the body-floating SOI device is lower than that of the body-tied one because of parasitic bipolar action. Soft-error testing by using 0.18 μm 4 Mbit static random-access memory (SRAM) indicates that the body-tied SOI devices with the PTI structure have high soft-error tolerance as compared with bulk devices. The charge collections for the PTI structure are also investigated to mitigate the soft errors. It is demonstrated that the body-tied PTI SOI technology is one of the best solutions for high-performance system LSIs with high soft-error tolerance.

• 2008-01-25

著者

• Inoue Yasuo

  Process Technology Development Div. Renesas Technology Corp.

• Ipposhi Takashi

  Process Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Nii Koji

  Design Technology Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Sonoda Kenichiro

  Process Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Hirano Yuuichi

  Process Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Iwamatsu Toshiaki

  Process Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Shiga Katsuya

  Process Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Maegawa Shigeto

  Process Technology Development Division, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

関連論文

• Study of Stress from Discontinuous SiN Liner for Fully-Silicided Gate Process
• High Soft-Error Tolerance Body-Tied Silicon-on-Insulator Technology with Partial Trench Isolation
• Layout-Independent Transistor with Stress-Controlled and Highly Manufacturable Shallow Trench Isolation Process

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