A Low-Power, Small-Size 10-Bit Successive-Approximation ADC(Analog Signal Processing)
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概要
- 論文の詳細を見る
A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2μm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67dB SFDR. Power consumption and die area are 0.6mW and 0.95mm^2, respectively. ADC was extensively simulated using Hspice to verify the desired performance.
- 社団法人電子情報通信学会の論文
- 2005-04-01
著者
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Hadidi Khayrollah
Microelectronic Research Laboratory Urmia University
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Hadidi Khayrollah
Urmia Univ. Urmia Irn
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KHOEI Abdollah
Microelectronic research laboratory, Urmia University
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BANIHASHEMI Mehdi
Microelectronics Research Laboratory, Urmia University
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Khoei Abdollah
Urmia Univ. Urmia Irn
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Banihashemi Mehdi
Microelectronics Research Laboratory Urmia University
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Hadidi Khayrollah
Microelectronic Research Laboratory Of Urmia University
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Khoei Abdollah
Microelectronic Research Laboratory Of Urmia University
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